This invention concerns the technical field of frequency synthesizers; specifically, it concerns a frequency synthesizer that can suppress the generation of spurious components.
Frequency synthesizers that employ a fractional frequency division type PLL circuit are known as circuits that can yield signals of the desired frequency and pull in frequencies at high speed. At present, for example, frequency synthesizers have been realized that can pull in a frequency in 300 microseconds or less even if the channel interval in the 800-MHz band is set to 25 kHz. In integer frequency division PLL, this can be called a major feature, as against a limit of only about 1.5 milliseconds at most. With regard to phase noise characteristics as well, it is about 10-20 dB better with respect to the integer type.
Such performance has made frequency synthesizers that employ fractional frequency division type PLL circuits indispensable devices in the field of wireless communication.
Symbol 101 in FIG. 4 is an example of a conventional-technology frequency synthesizer that employs the fractional frequency division method; it has oscillator 131, frequency divider 132, clock generator 133, phase comparator 134, charge pump circuit 135, low-pass filter 136, compensation circuit 137, and frequency division value setting circuit 138.
Formed from these circuits is a negative feedback loop as described below; it is composed in such a way that signals output from the charge pump circuit are input via low-pass filter 136 into oscillator 131, output signal OUT of a frequency corresponding to the size of the signal is output to external circuits and frequency divider 132.
To describe the negative feedback loop of this frequency synthesizer 101, first, output signal OUT output by oscillator 131 is input into frequency divider 132, output signal OUT is frequency-divided by the integer frequency division value set inside frequency divider 132, and the frequency-divided signal is input into phase comparator 134.
Phase comparator 134 inputs the frequency-divided signal and the basic clock signal output by clock generator 133, generates a signal that corresponds to the phase difference between the two signals, and outputs it to charge pump circuit 135.
Charge pump circuit 135 is constituted so as to output a fixed current just for the time corresponding to the signal input from phase comparator 134, and the signal according to this fixed current is input through low-pass filter 136 into oscillator 131.
If the signal output by charge pump circuit 135 indicates that the frequency of the output signal of frequency divider 132 is higher than the frequency of the standard clock signal, oscillator 132 will lower the frequency of output signal OUT, and conversely, if it indicates that the frequency of the output signal of frequency divider 132 is lower than the frequency of the standard clock signal, it will raise the frequency of output signal OUT.
As a result, oscillator 131 operates so as to make the error signal output by phase comparator 134 small, so that overall a negative feedback loop is formed, and output signal OUT remains stable at the prescribed frequency.
The frequency division value set inside said frequency divider 132 is an integer frequency division value, but the size of the integer frequency division value is controlled by frequency division value setting circuit 138, and the construction is such that the value changes periodically. As a result of the integer frequency division value changing periodically, the value to which the integer frequency division values are averaged becomes the fractional frequency division value, so a signal is obtained of a frequency that is a fractional frequency division value multiple of the standard clock signal.
For example, if (5000+xe2x85x9) is necessary as the fractional frequency division value, then the value that is the average of the integer frequency division values during the time period of 8 periods, that is, the fractional frequency division value becomes (5000+xe2x85x9) if, during eight continuous periods of the standard clock signal, the integer frequency division value is set to 5000 for just 7 periods, and the integer frequency division value is set to 5001 for the remaining 1 period.
In this case, because the integer frequency division value changes, the output voltage of charge pump 135 constantly changes, but the output of charge pump 135 is averaged by low-pass filter 136, so when the 8-period time period is averaged, the frequency of the signal output by frequency divider 132 and the frequency of the standard clock signal will agree. As a result, the frequency of output signal OUT of oscillator 131 will be stable at a value that is fractional frequency division value (5000+xe2x85x9) times the standard clock signal.
But because the integer frequency division value changes as described above, even if output signal OUT is stable, the phase of the signal output by frequency divider 132 and the phase of the standard clock will never agree completely. Therefore every time phase comparator 134 operates, an error signal is output from phase comparator 134 (depending on the value of the fractional frequency division value, there may be a period during which no error signal is output, even if phase comparator 134 operates), and a ripple current of a size that corresponds to the phase difference is output from charge pump circuit 135.
To describe this ripple current, FIG. 5(a) is a timing chart of output signal OUT of frequency divider 132 versus the standard clock signal in the case when the fractional frequency division value is (5000+xe2x85x9). Symbol CLK in this diagram denotes the timing of the standard clock signal, and symbols T1-T8 denote phases of output signal OUT of frequency divider 132.
W1-W8 express the amount of phase error between phases T1-T8 of each output signal OUT of frequency divider 132 and standard clock signal CLK. These error amounts W1-W8 include delay error amounts W1-W4 and advance error amounts W5-W8, but the total value of the delay error amounts W1-W4 and the total value of the advance error amounts W5-W8 are equal. Therefore, as described above, when the phase of output signal OUT is time-period averaged for 8 periods, it is equal to the phase of standard clock signal CLK.
Symbols R1-R8 in FIG. 5(b) denote the output time periods of the ripple current that is output from charge pump circuit 135 when said phase error amounts W1-W8 arise. Because charge pump circuit 135 is a fixed current output, the amount of electric charge of the respective ripple currents is proportional to the output time period. Denoting by +/xe2x88x92q the amount of electric charge of the ripple current at minimum error amounts W4 and W5, the amount of electric charge of the ripple currents corresponding to error amounts W1-W8 is xe2x88x927 q, xe2x88x925 q, xe2x88x923 q, xe2x88x92q, q, 3 q, 5 q, 7 q.
The timing and size by which such ripple current is output has a period that corresponds to the period of the integer frequency division value, so there is the problem that spurious components arise on output signal OUT.
Thus, in order to eliminate such spurious components, measures are taken even with conventional-technology frequency synthesizer 101; they are controlled by frequency division value setting circuit 138, compensation circuit 137 is provided, and by the timing by which ripple currents are output from charge pump circuit 135, a compensation current is generated that is opposite the ripple current in polarity but equal in size, and this is superimposed on output signal OUT of charge pump circuit 135, thereby eliminating the ripple current.
Symbols C1-C8 in FIG. 5(b) denote the charge amount of the compensation currents corresponding to the charge amounts R1-R8 of the ripple currents. The charge amount of compensation currents C1-C8 are 7 q, 5 q, 3 q, q, xe2x88x92q, xe2x88x923 q, xe2x88x925 q, xe2x88x927 q.
But because of such causes as variability in manufacture, with conventional-technology frequency synthesizer 101 it is difficult to ensure that the amount of electric charge of the compensation currents agrees completely with the amount of electric charge of the ripple currents. Therefore there are cases in which the ripple current cannot be completely eliminated.
If the ripple current cannot be eliminated completely, its effect will have periodicity, so spurious components will remain in output signal OUT. Taking manufacturing variability into consideration, the rate of reduction in spurious components by compensation circuit 137 will vary in a range of about 40 dB to 30 dB.
A general purpose of this invention, which was created in order to solve the above drawbacks of the conventional technology, is to provide technology by which the rate of reduction of spurious components can be increased.
According to one aspect of the invention, the frequency synthesizer of this invention has an oscillator that controls the frequency of an oscillation signal in accordance with a control signal, a fractional frequency division type frequency divider that frequency-divides said oscillation signal and generates a comparison signal, a standard clock signal generator that generates a standard clock signal, a phase comparator that compares the phase of said comparison signal and the phase of said standard clock signal and outputs a phase difference signal, a charge pump circuit that outputs a current in accordance with said phase difference signal, a low-pass filter that eliminates the higher harmonics of the current that is output from said charge pump circuit and supplies it to said oscillator as said control signal, a compensation circuit that supplies to the output terminal of said charge pump circuit a compensation current for compensating the ripple current included in said control signal, and a frequency division value setting circuit that nonperiodically alters the frequency division value of said frequency divider.
Another aspect of this invention is a frequency synthesizer as described above in which said frequency division value setting circuit has a random number generator and a frequency division value control circuit that, based on random numbers generated by said random number generator, determines integer frequency division values for determining the fractional frequency division value of said frequency divider and outputs said integer frequency division value to said frequency divider.
A further aspect of this invention is a frequency synthesizer as described above in which the integer frequency division values output to said frequency divider are controlled so as to be within the prescribed range.
With this invention, being comprised as describe above, periodicity does not appear when the integer frequency division values for making fractional frequency division values are changed. Therefore, spurious components of the output signal caused by ripple current do not arise.
Even if a compensation current is superimposed on the output of the charge pump circuit and the ripple current is eliminated, the effect of the ripple current will remain, but even in that case, there is no periodicity in the effect of the ripple current, so no spurious components will arise in the output signal.
Because the capacity of the compensation circuit imposes restrictions on the size of the compensation current that can be generated, in this invention the integer frequency division values are controlled so that when the integer frequency division value is changed, the phase difference between the frequency of the signal obtained by integer-frequency-dividing the output signal and the standard clock signal does not exceed the capacity of the compensation current.